This subproject is one of many research subprojects utilizing the resources provided by a Center grant funded by NIH/NCRR. Primary support for the subproject and the subproject's principal investigator may have been provided by other sources, including other NIH sources. The Total Cost listed for the subproject likely represents the estimated amount of Center infrastructure utilized by the subproject, not direct funding provided by the NCRR grant to the subproject or subproject staff. For the most of our pulsed ESR spectrometers we do not need long data records except for the special case of the kinetic form of 1D/2D FT ESR where we plan to use an Acqiris ADC with its powerful high-throughput averaging capacity entailing multi-segment round-robin features. For standard 2D-ELDOR applications and DQC/DEER, a fast limited-size on-chip memory of modern FPGAs is sufficient. Furthermore, the dual-ported nature of such memories and on-chip high-speed serial links permit data transfers to the host PC for visualization without unnecessary intervention into the data acquisition cycle. Both, I and Q incoming data can be processed in a single FPGA simultaneously as prescribed by the downloaded receiver phase tables. The ADC of choice is AD9203 250 Msps used in pairs (more flexibility) or AD12501 500 Msps connectorized modules (ready to go) from Analog Devices featuring 1-350 MHz analog bandwidth. Properly buffered LVDS outputs can be directly connected to a suitable FPGA housed in its own module;this configuration is able to reduce baseline drift due to coherent pickup caused by interference at harmonics of FPGA clock frequency as is the case e.g. with the Acqiris averager.